6502 Instruction Set

Bits Mode Bits Condition
000[[xx + X]]000PL
001[xx]001MI
010#xx010VC
011[xxxx]011VS
100[[xx] + Y]100CC
101[xx + X]101CS
110[xxxx + Y]110NE
111[xxxx + X]111EQ

ADC

A = A + M + C

Opcode Instruction Size Cycles Flags
011 mode 01ADC M  N Z C V
61ADC [[xx + X]]26N Z C V
65ADC [xx]23N Z C V
69ADC #xx22N Z C V
6DADC [xxxx]34N Z C V
71ADC [[xx] + Y]25*N Z C V
75ADC [xx + X]24N Z C V
79ADC [xxxx + Y]34*N Z C V
7DADC [xxxx + X]34*N Z C V

AND

A = A & M

Opcode Instruction Size Cycles Flags
001 mode 01AND M  N Z
21AND [[xx + X]]26N Z
25AND [xx]23N Z
29AND #xx22N Z
2DAND [xxxx]34N Z
31AND [[xx] + Y]25*N Z
35AND [xx + X]24N Z
39AND [xxxx + Y]34*N Z
3DAND [xxxx + X]34*N Z

ASL

C = M[7], M = M << 1

Opcode Instruction Size Cycles Flags
000 mode 10ASL M  N Z C
02undef--N Z C
06ASL [xx]25N Z C
0AASL A12N Z C
0EASL [xxxx]36N Z C
12undef--N Z C
16ASL [xx + X]26N Z C
1Aundef--N Z C
1EASL [xxxx + X]37N Z C

Bcc

Branch on condition true

Opcode Instruction Size Cycles Flags
cond 10000Bcc xx22* 
10BPL xx22* 
30BMI xx22* 
50BVC xx22* 
70BVS xx22* 
90BCC xx22* 
B0BCS xx22* 
D0BNE xx22* 
F0BEQ xx22* 

BIT

N = (A & M)[7], V = (A & M)[6]

Opcode Instruction Size Cycles Flags
24BIT [xx]23N Z V
2CBIT [xxxx]34N Z V

BRK

Forced interrupt
Opcode Instruction Size Cycles Flags
00BRK17I

CLC

C = 0

Opcode Instruction Size Cycles Flags
18CLC12C

CLD

D = 0

Opcode Instruction Size Cycles Flags
D8CLD12D

CLI

I = 0

Opcode Instruction Size Cycles Flags
58CLI12I

CLV

V = 0

Opcode Instruction Size Cycles Flags
B8CLV12V

CMP

A - M

Opcode Instruction Size Cycles Flags
110 mode 01CMP M  N Z C
C1CMP [[xx + X]]26N Z C
C5CMP [xx]23N Z C
C9CMP #xx22N Z C
CDCMP [xxxx]34N Z C
D1CMP [[xx] + Y]25*N Z C
D5CMP [xx + X]24N Z C
D9CMP [xxxx + Y]34*N Z C
DDCMP [xxxx + X]34*N Z C

CPX

X - M

Opcode Instruction Size Cycles Flags
E0CPX #xx22N Z C
E4CPX [xx]23N Z C
ECCPX [xxxx]34N Z C

CPY

Y - M

Opcode Instruction Size Cycles Flags
C0CPY #xx22N Z C
C4CPY [xx]23N Z C
CCCPY [xxxx]34N Z C

DEC

M = M - 1

Opcode Instruction Size Cycles Flags
110 mode 10DEC M  N Z
C2undef---
C6DEC [xx]25N Z
CADEX12N Z
CEDEC [xxxx]36N Z
D2undef---
D6DEC [xx + X]26N Z
DAundef---
DEDEC [xxxx + X]37N Z

DEX

X = X - 1

Opcode Instruction Size Cycles Flags
CADEX12N Z

DEY

Y = Y - 1

Opcode Instruction Size Cycles Flags
88DEY12N Z

EOR

A = A ^ M

Opcode Instruction Size Cycles Flags
010 mode 01EOR M  N Z
41EOR [[xx + X]]26N Z
45EOR [xx]23N Z
49EOR #xx22N Z
4DEOR [xxxx]34N Z
51EOR [[xx] + Y]25*N Z
55EOR [xx + X]24N Z
59EOR [xxxx + Y]34*N Z
5DEOR [xxxx + X]34*N Z

INC

M = M + 1
Opcode Instruction Size Cycles Flags
111 mode 10 INC M

N Z
E2 undef - - -
E6 INC [xx] 2 5 N Z
EA NOP 1 2
EE INC [xxxx] 3 6 N Z
F2 undef - - -
F6 INC [xx + X] 2 6 N Z
FA undef - - -
FE INC [xxxx + X] 3 7 N Z

INX

X = X + 1
Opcode Instruction Size Cycles Flags
E8 INX 1 2 N Z

INY

Y = Y + 1
Opcode Instruction Size Cycles Flags
C8 INY 1 2 N Z

JMP

Jump
Opcode Instruction Size Cycles Flags
4C JMP xxxx 3 3
6C JMP [xxxx] 3 5

JSR

Jump to subroutine
Opcode Instruction Size Cycles Flags
20 JSR xxxx 3 6

LDA

A = M
Opcode Instruction Size Cycles Flags
101 mode 01 LDA M

N Z
A1 LDA [[xx + X]] 2 6 N Z
A5 LDA [xx] 2 3 N Z
A9 LDA #xx 2 2 N Z
AD LDA [xxxx] 3 4 N Z
B1 LDA [[xx] + Y] 2 5* N Z
B5 LDA [xx + X] 2 4 N Z
B9 LDA [xxxx + Y] 3 4* N Z
BD LDA [xxxx + X] 3 4* N Z

LDX

X = M
Opcode Instruction Size Cycles Flags
A2 LDX #xx 2 2 N Z
A6 LDX [xx] 2 3 N Z
AE LDX [xxxx] 3 4 N Z
B6 LDX [xx + Y] 2 4 N Z
BE LDX [xxxx + Y] 3 4* N Z

LDY

Y = M
Opcode Instruction Size Cycles Flags
A0 LDY #xx 2 2 N Z
A4 LDY [xx] 2 3 N Z
AC LDY [xxxx] 3 4 N Z
B4 LDY [xx + X] 2 4 N Z
BC LDY [xxxx + X] 3 4* N Z

LSR

C = M[0], M = M >> 1
Opcode Instruction Size Cycles Flags
010 mode 10 LSR M

N Z C
42 undef - - -
46 LSR [xx] 2 5 N Z C
4A LSR A 1 2 N Z C
4E LSR [xxxx] 3 6 N Z C
52 undef - - -
56 LSR [xx + X] 2 6 N Z C
5A undef - - -
5E LSR [xxxx + X] 3 7 N Z C

NOP

No operation
Opcode Instruction Size Cycles Flags
EA NOP 1 2

ORA

A = A | M
Opcode Instruction Size Cycles Flags
000 mode 01 ORA M

N Z
01 ORA [[xx + X]] 2 6 N Z
05 ORA [xx] 2 3 N Z
09 ORA #xx 2 2 N Z
0D ORA [xxxx] 3 4 N Z
11 ORA [[xx] + Y] 2 5 N Z
15 ORA [xx + X] 2 4 N Z
19 ORA [xxxx + Y] 3 4* N Z
1D ORA [xxxx + X] 3 4* N Z

PHA

Push A
Opcode Instruction Size Cycles Flags
48 PHA 1 3

PHP

Push P
Opcode Instruction Size Cycles Flags
08 PHP 1 3

PLA

Pop A
Opcode Instruction Size Cycles Flags
68 PLA 1 4

PLP

Pop A
Opcode Instruction Size Cycles Flags
28 PLP 1 4 N Z C I D V

ROL

T = M[7], M = (M << 1) + C, C = T
Opcode Instruction Size Cycles Flags
001 mode 10 ROL M

N Z C
22 undef - - -
26 ROL [xx] 2 5 N Z C
2A ROL A 1 2 N Z C
2E ROL [xxxx] 3 6 N Z C
32 undef - - -
36 ROL [xx + X] 2 6 N Z C
3A undef - - -
3E ROL [xxxx + X] 3 7 N Z C

ROR

T = M[0], M = (M >> 1) + (C << 7), C = T
Opcode Instruction Size Cycles Flags
011 mode 10 ROR M

N Z C
62 undef - - -
66 ROR [xx] 2 5 N Z C
6A ROR A 1 2 N Z C
6E ROR [xxxx] 3 6 N Z C
72 undef - - -
76 ROR [xx + X] 2 6 N Z C
7A undef - - -
7E ROR [xxxx + X] 3 7 N Z C

RTI

Return from interrupt
Opcode Instruction Size Cycles Flags
40 RTI 1 6

RTS

Return from subroutine
Opcode Instruction Size Cycles Flags
60RTS16 

SBC

A = A - M - ~C
Opcode Instruction Size Cycles Flags
111 mode 01 SBC M

N Z C V
E1 SBC [[xx + X]] 2 6 N Z C V
E5 SBC [xx] 2 3 N Z C V
E9 SBC #xx 2 2 N Z C V
ED SBC [xxxx] 3 4 N Z C V
F1 SBC [[xx] + Y] 2 5* N Z C V
F5 SBC [xx + X] 2 4 N Z C V
F9 SBC [xxxx + Y] 3 4* N Z C V
FD SBC [xxxx + X] 3 4* N Z C V

SEC

C = 1
Opcode Instruction Size Cycles Flags
38SEC12C

SED

D = 1
Opcode Instruction Size Cycles Flags
F8 SED 1 2 D

SEI

I = 1
Opcode Instruction Size Cycles Flags
78 SEI 1 2 I

STA

M = A
Opcode Instruction Size Cycles Flags
100 mode 01 STA M


81 STA [[xx + X]] 2 6
85 STA [xx] 2 3
89 undef - - -
8D STA [xxxx] 3 4
91 STA [[xx] + Y] 2 6
95 STA [xx + X] 2 4
99 STA [xxxx + Y] 3 5
9D STA [xxxx + X] 3 5

STX

M = X
Opcode Instruction Size Cycles Flags
86 STX [xx] 2 3
8E STX [xxxx] 3 4
96 STX [xx + Y] 2 4

STY

M = Y
Opcode Instruction Size Cycles Flags
84 STY [xx] 2 3
8C STY [xxxx] 3 4
94 STY [xx + X] 2 4

TAX

X = A

Opcode Instruction Size Cycles Flags
AATAX12N Z

TAY

Y = A

Opcode Instruction Size Cycles Flags
A8TAY12N Z

TSX

X = S

Opcode Instruction Size Cycles Flags
BATSX12N Z

TXA

A = X

Opcode Instruction Size Cycles Flags
8ATXA12N Z

TXS

S = X

Opcode Instruction Size Cycles Flags
9ATXS12 

TYA

A = Y

Opcode Instruction Size Cycles Flags
98TYA12N Z