6502 Instruction Set
Bits |
Mode |
|
Bits |
Condition |
000 | [[xx + X]] | | 000 | PL |
001 | [xx] | | 001 | MI |
010 | #xx | | 010 | VC |
011 | [xxxx] | | 011 | VS |
100 | [[xx] + Y] | | 100 | CC |
101 | [xx + X] | | 101 | CS |
110 | [xxxx + Y] | | 110 | NE |
111 | [xxxx + X] | | 111 | EQ |
ADC
A = A + M + C
Opcode |
Instruction |
Size |
Cycles |
Flags |
011 mode 01 | ADC M | | | N Z C V |
61 | ADC [[xx + X]] | 2 | 6 | N Z C V |
65 | ADC [xx] | 2 | 3 | N Z C V |
69 | ADC #xx | 2 | 2 | N Z C V |
6D | ADC [xxxx] | 3 | 4 | N Z C V |
71 | ADC [[xx] + Y] | 2 | 5* | N Z C V |
75 | ADC [xx + X] | 2 | 4 | N Z C V |
79 | ADC [xxxx + Y] | 3 | 4* | N Z C V |
7D | ADC [xxxx + X] | 3 | 4* | N Z C V |
AND
A = A & M
Opcode |
Instruction |
Size |
Cycles |
Flags |
001 mode 01 | AND M | | | N Z |
21 | AND [[xx + X]] | 2 | 6 | N Z |
25 | AND [xx] | 2 | 3 | N Z |
29 | AND #xx | 2 | 2 | N Z |
2D | AND [xxxx] | 3 | 4 | N Z |
31 | AND [[xx] + Y] | 2 | 5* | N Z |
35 | AND [xx + X] | 2 | 4 | N Z |
39 | AND [xxxx + Y] | 3 | 4* | N Z |
3D | AND [xxxx + X] | 3 | 4* | N Z |
ASL
C = M[7], M = M << 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
000 mode 10 | ASL M | | | N Z C |
02 | undef | - | - | N Z C |
06 | ASL [xx] | 2 | 5 | N Z C |
0A | ASL A | 1 | 2 | N Z C |
0E | ASL [xxxx] | 3 | 6 | N Z C |
12 | undef | - | - | N Z C |
16 | ASL [xx + X] | 2 | 6 | N Z C |
1A | undef | - | - | N Z C |
1E | ASL [xxxx + X] | 3 | 7 | N Z C |
Bcc
Branch on condition true
Opcode |
Instruction |
Size |
Cycles |
Flags |
cond 10000 | Bcc xx | 2 | 2* | |
10 | BPL xx | 2 | 2* | |
30 | BMI xx | 2 | 2* | |
50 | BVC xx | 2 | 2* | |
70 | BVS xx | 2 | 2* | |
90 | BCC xx | 2 | 2* | |
B0 | BCS xx | 2 | 2* | |
D0 | BNE xx | 2 | 2* | |
F0 | BEQ xx | 2 | 2* | |
BIT
N = (A & M)[7], V = (A & M)[6]
Opcode |
Instruction |
Size |
Cycles |
Flags |
24 | BIT [xx] | 2 | 3 | N Z V |
2C | BIT [xxxx] | 3 | 4 | N Z V |
BRK
Forced interrupt
Opcode |
Instruction |
Size |
Cycles |
Flags |
00 | BRK | 1 | 7 | I |
CLC
C = 0
Opcode |
Instruction |
Size |
Cycles |
Flags |
18 | CLC | 1 | 2 | C |
CLD
D = 0
Opcode |
Instruction |
Size |
Cycles |
Flags |
D8 | CLD | 1 | 2 | D |
CLI
I = 0
Opcode |
Instruction |
Size |
Cycles |
Flags |
58 | CLI | 1 | 2 | I |
CLV
V = 0
Opcode |
Instruction |
Size |
Cycles |
Flags |
B8 | CLV | 1 | 2 | V |
CMP
A - M
Opcode |
Instruction |
Size |
Cycles |
Flags |
110 mode 01 | CMP M | | | N Z C |
C1 | CMP [[xx + X]] | 2 | 6 | N Z C |
C5 | CMP [xx] | 2 | 3 | N Z C |
C9 | CMP #xx | 2 | 2 | N Z C |
CD | CMP [xxxx] | 3 | 4 | N Z C |
D1 | CMP [[xx] + Y] | 2 | 5* | N Z C |
D5 | CMP [xx + X] | 2 | 4 | N Z C |
D9 | CMP [xxxx + Y] | 3 | 4* | N Z C |
DD | CMP [xxxx + X] | 3 | 4* | N Z C |
CPX
X - M
Opcode |
Instruction |
Size |
Cycles |
Flags |
E0 | CPX #xx | 2 | 2 | N Z C |
E4 | CPX [xx] | 2 | 3 | N Z C |
EC | CPX [xxxx] | 3 | 4 | N Z C |
CPY
Y - M
Opcode |
Instruction |
Size |
Cycles |
Flags |
C0 | CPY #xx | 2 | 2 | N Z C |
C4 | CPY [xx] | 2 | 3 | N Z C |
CC | CPY [xxxx] | 3 | 4 | N Z C |
DEC
M = M - 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
110 mode 10 | DEC M | | | N Z |
C2 | undef | - | - | - |
C6 | DEC [xx] | 2 | 5 | N Z |
CA | DEX | 1 | 2 | N Z |
CE | DEC [xxxx] | 3 | 6 | N Z |
D2 | undef | - | - | - |
D6 | DEC [xx + X] | 2 | 6 | N Z |
DA | undef | - | - | - |
DE | DEC [xxxx + X] | 3 | 7 | N Z |
DEX
X = X - 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
CA | DEX | 1 | 2 | N Z |
DEY
Y = Y - 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
88 | DEY | 1 | 2 | N Z |
EOR
A = A ^ M
Opcode |
Instruction |
Size |
Cycles |
Flags |
010 mode 01 | EOR M | | | N Z |
41 | EOR [[xx + X]] | 2 | 6 | N Z |
45 | EOR [xx] | 2 | 3 | N Z |
49 | EOR #xx | 2 | 2 | N Z |
4D | EOR [xxxx] | 3 | 4 | N Z |
51 | EOR [[xx] + Y] | 2 | 5* | N Z |
55 | EOR [xx + X] | 2 | 4 | N Z |
59 | EOR [xxxx + Y] | 3 | 4* | N Z |
5D | EOR [xxxx + X] | 3 | 4* | N Z |
INC
M = M + 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
111 mode 10
|
INC M
|
|
|
N Z
|
E2
|
undef
|
-
|
-
|
-
|
E6
|
INC [xx]
|
2
|
5
|
N Z
|
EA
|
NOP
|
1
|
2
|
|
EE
|
INC [xxxx]
|
3
|
6
|
N Z
|
F2
|
undef
|
-
|
-
|
-
|
F6
|
INC [xx + X]
|
2
|
6
|
N Z
|
FA
|
undef
|
-
|
-
|
-
|
FE
|
INC [xxxx + X]
|
3
|
7
|
N Z
|
INX
X = X + 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
E8
|
INX
|
1
|
2
|
N Z
|
INY
Y = Y + 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
C8
|
INY
|
1
|
2
|
N Z
|
JMP
Jump
Opcode |
Instruction |
Size |
Cycles |
Flags |
4C
|
JMP xxxx
|
3
|
3
|
|
6C
|
JMP [xxxx]
|
3
|
5
|
|
JSR
Jump to subroutine
Opcode |
Instruction |
Size |
Cycles |
Flags |
20
|
JSR xxxx
|
3
|
6
|
|
LDA
A = M
Opcode |
Instruction |
Size |
Cycles |
Flags |
101 mode 01
|
LDA M
|
|
|
N Z
|
A1
|
LDA [[xx + X]]
|
2
|
6
|
N Z
|
A5
|
LDA [xx]
|
2
|
3
|
N Z
|
A9
|
LDA #xx
|
2
|
2
|
N Z
|
AD
|
LDA [xxxx]
|
3
|
4
|
N Z
|
B1
|
LDA [[xx] + Y]
|
2
|
5*
|
N Z
|
B5
|
LDA [xx + X]
|
2
|
4
|
N Z
|
B9
|
LDA [xxxx + Y]
|
3
|
4*
|
N Z
|
BD
|
LDA [xxxx + X]
|
3
|
4*
|
N Z
|
LDX
X = M
Opcode |
Instruction |
Size |
Cycles |
Flags |
A2
|
LDX #xx
|
2
|
2
|
N Z
|
A6
|
LDX [xx]
|
2
|
3
|
N Z
|
AE
|
LDX [xxxx]
|
3
|
4
|
N Z
|
B6
|
LDX [xx + Y]
|
2
|
4
|
N Z
|
BE
|
LDX [xxxx + Y]
|
3
|
4*
|
N Z
|
LDY
Y = M
Opcode |
Instruction |
Size |
Cycles |
Flags |
A0
|
LDY #xx
|
2
|
2
|
N Z
|
A4
|
LDY [xx]
|
2
|
3
|
N Z
|
AC
|
LDY [xxxx]
|
3
|
4
|
N Z
|
B4
|
LDY [xx + X]
|
2
|
4
|
N Z
|
BC
|
LDY [xxxx + X]
|
3
|
4*
|
N Z
|
LSR
C = M[0], M = M >> 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
010 mode 10
|
LSR M
|
|
|
N Z C
|
42
|
undef
|
-
|
-
|
-
|
46
|
LSR [xx]
|
2
|
5
|
N Z C
|
4A
|
LSR A
|
1
|
2
|
N Z C
|
4E
|
LSR [xxxx]
|
3
|
6
|
N Z C
|
52
|
undef
|
-
|
-
|
-
|
56
|
LSR [xx + X]
|
2
|
6
|
N Z C
|
5A
|
undef
|
-
|
-
|
-
|
5E
|
LSR [xxxx + X]
|
3
|
7
|
N Z C
|
NOP
No operation
Opcode |
Instruction |
Size |
Cycles |
Flags |
EA
|
NOP
|
1
|
2
|
|
ORA
A = A | M
Opcode |
Instruction |
Size |
Cycles |
Flags |
000 mode 01
|
ORA M
|
|
|
N Z
|
01
|
ORA [[xx + X]]
|
2
|
6
|
N Z
|
05
|
ORA [xx]
|
2
|
3
|
N Z
|
09
|
ORA #xx
|
2
|
2
|
N Z
|
0D
|
ORA [xxxx]
|
3
|
4
|
N Z
|
11
|
ORA [[xx] + Y]
|
2
|
5
|
N Z
|
15
|
ORA [xx + X]
|
2
|
4
|
N Z
|
19
|
ORA [xxxx + Y]
|
3
|
4*
|
N Z
|
1D
|
ORA [xxxx + X]
|
3
|
4*
|
N Z
|
PHA
Push A
Opcode |
Instruction |
Size |
Cycles |
Flags |
48
|
PHA
|
1
|
3
|
|
PHP
Push P
Opcode |
Instruction |
Size |
Cycles |
Flags |
08
|
PHP
|
1
|
3
|
|
PLA
Pop A
Opcode |
Instruction |
Size |
Cycles |
Flags |
68
|
PLA
|
1
|
4
|
|
PLP
Pop A
Opcode |
Instruction |
Size |
Cycles |
Flags |
28
|
PLP
|
1
|
4
|
N Z C I D V
|
ROL
T = M[7], M = (M << 1) + C, C = T
Opcode |
Instruction |
Size |
Cycles |
Flags |
001 mode 10
|
ROL M
|
|
|
N Z C
|
22
|
undef
|
-
|
-
|
-
|
26
|
ROL [xx]
|
2
|
5
|
N Z C
|
2A
|
ROL A
|
1
|
2
|
N Z C
|
2E
|
ROL [xxxx]
|
3
|
6
|
N Z C
|
32
|
undef
|
-
|
-
|
-
|
36
|
ROL [xx + X]
|
2
|
6
|
N Z C
|
3A
|
undef
|
-
|
-
|
-
|
3E
|
ROL [xxxx + X]
|
3
|
7
|
N Z C
|
ROR
T = M[0], M = (M >> 1) + (C << 7), C = T
Opcode |
Instruction |
Size |
Cycles |
Flags |
011 mode 10
|
ROR M
|
|
|
N Z C
|
62
|
undef
|
-
|
-
|
-
|
66
|
ROR [xx]
|
2
|
5
|
N Z C
|
6A
|
ROR A
|
1
|
2
|
N Z C
|
6E
|
ROR [xxxx]
|
3
|
6
|
N Z C
|
72
|
undef
|
-
|
-
|
-
|
76
|
ROR [xx + X]
|
2
|
6
|
N Z C
|
7A
|
undef
|
-
|
-
|
-
|
7E
|
ROR [xxxx + X]
|
3
|
7
|
N Z C
|
RTI
Return from interrupt
Opcode |
Instruction |
Size |
Cycles |
Flags |
40
|
RTI
|
1
|
6
|
|
RTS
Return from subroutine
Opcode |
Instruction |
Size |
Cycles |
Flags |
60 | RTS | 1 | 6 | |
SBC
A = A - M - ~C
Opcode |
Instruction |
Size |
Cycles |
Flags |
111 mode 01
|
SBC M
|
|
|
N Z C V
|
E1
|
SBC [[xx + X]]
|
2
|
6
|
N Z C V
|
E5
|
SBC [xx]
|
2
|
3
|
N Z C V
|
E9
|
SBC #xx
|
2
|
2
|
N Z C V
|
ED
|
SBC [xxxx]
|
3
|
4
|
N Z C V
|
F1
|
SBC [[xx] + Y]
|
2
|
5*
|
N Z C V
|
F5
|
SBC [xx + X]
|
2
|
4
|
N Z C V
|
F9
|
SBC [xxxx + Y]
|
3
|
4*
|
N Z C V
|
FD
|
SBC [xxxx + X]
|
3
|
4*
|
N Z C V
|
SEC
C = 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
38 | SEC | 1 | 2 | C |
SED
D = 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
F8
|
SED
|
1
|
2
|
D
|
SEI
I = 1
Opcode |
Instruction |
Size |
Cycles |
Flags |
78
|
SEI
|
1
|
2
|
I
|
STA
M = A
Opcode |
Instruction |
Size |
Cycles |
Flags |
100 mode 01
|
STA M
|
|
|
|
81
|
STA [[xx + X]]
|
2
|
6
|
|
85
|
STA [xx]
|
2
|
3
|
|
89
|
undef
|
-
|
-
|
-
|
8D
|
STA [xxxx]
|
3
|
4
|
|
91
|
STA [[xx] + Y]
|
2
|
6
|
|
95
|
STA [xx + X]
|
2
|
4
|
|
99
|
STA [xxxx + Y]
|
3
|
5
|
|
9D
|
STA [xxxx + X]
|
3
|
5
|
|
STX
M = X
Opcode |
Instruction |
Size |
Cycles |
Flags |
86
|
STX [xx]
|
2
|
3
|
|
8E
|
STX [xxxx]
|
3
|
4
|
|
96
|
STX [xx + Y]
|
2
|
4
|
|
STY
M = Y
Opcode |
Instruction |
Size |
Cycles |
Flags |
84
|
STY [xx]
|
2
|
3
|
|
8C
|
STY [xxxx]
|
3
|
4
|
|
94
|
STY [xx + X]
|
2
|
4
|
|
TAX
X = A
Opcode |
Instruction |
Size |
Cycles |
Flags |
AA | TAX | 1 | 2 | N Z |
TAY
Y = A
Opcode |
Instruction |
Size |
Cycles |
Flags |
A8 | TAY | 1 | 2 | N Z |
TSX
X = S
Opcode |
Instruction |
Size |
Cycles |
Flags |
BA | TSX | 1 | 2 | N Z |
TXA
A = X
Opcode |
Instruction |
Size |
Cycles |
Flags |
8A | TXA | 1 | 2 | N Z |
TXS
S = X
Opcode |
Instruction |
Size |
Cycles |
Flags |
9A | TXS | 1 | 2 | |
TYA
A = Y
Opcode |
Instruction |
Size |
Cycles |
Flags |
98 | TYA | 1 | 2 | N Z |